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A Multiple-Stage Parallel Replica-Bitline Delay Addition Technique for Reducing Timing Variation of
  • ISSN号：1549-7747
  • 期刊名称：IEEE Transactions on Circuits and Systems II-Expre
  • 时间：2014.4
  • 页码：264-268
  • 相关项目：超低功耗射频收发系统理论及电路实现研究
作者： Wu, JianHui|Zhu, JiaFeng|Xia, YingCheng|Bai, Na|
同期刊论文项目
超低功耗射频收发系统理论及电路实现研究
期刊论文 23 会议论文 5
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