位置：成果数据库 > 期刊 > 期刊详情页
A high PSRR CMOS voltage reference with 1.2 V operation
  • ISSN号：0925-1030
  • 期刊名称：Analog Integrated Circuits and Signal Processing
  • 时间：2013.10
  • 页码：79-86
  • 相关项目：超低功耗射频收发系统理论及电路实现研究
作者： Chen, Chao|Shen, Haifeng|Huang, Chen|Liu, Hao|
同期刊论文项目
超低功耗射频收发系统理论及电路实现研究
期刊论文 23 会议论文 5
同项目期刊论文
150 mA LDO with self-adjusting frequency compensation scheme
A CMOS Switched Load Harmonic Rejection Mixer for DTV Tuner Applications
CMOS temperature compensated logarithmic converter based on master-slave control
Digital-domain dual-calibration for single-ended successive approximation register ADCs
A review of LC-based digitally controlled oscillator with high frequency resolution
A Multiple-Stage Parallel Replica-Bitline Delay Addition Technique for Reducing Timing Variation of
A MASH 1-1-1 Delta Sigma time-to-digital converter based on two-stage time quantization
A 2.4-GHz All-Digital PLL With a 1-ps Resolution 0.9-mW Edge-Interchanging-Based Stochastic TDC
A high-resolution stochastic time-to-digital converter with edge-interchange scheme
A 0.6 V passive mixer with high conversion gain in 65 nm CMOS process
A low-cost built-in self-test for CP-PLL based on TDC
A review of cmos time-to-digital converter
A Low-Power 2.4-GHz Receiver Front End With a Lateral Current-Reusing Technique
A 433 MHz ？104 dBm OOK/ASK receiver with the dynamic range of 95 dB in 0.18-μm CMOS process
A 1.2V high conversion gain mixer with reused gm stage in 65 nm CMOS
An active-RC reconfigurable lowpass-polyphase biquad filter for wireless receiver
Digital Background Calibration Techniques for Pipelined ADC Based on Comparator Dithering
A low-power high-speed true single phase clock divide-by-2/3 prescaler
A 1.5-V Current Mirror Double-Balanced Mixer With 10-dBm IIP3 and 9.5-dB Conversion Gain
常用变频泵组的工况分析及其选用建议
土地集约利用、资产增值与产业结构优化——基于DEA方法的实证研究