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Summarization of Boolean satisfiability verification
  • ISSN号:0217-9822
  • 期刊名称:Journal of Electronics(China)
  • 时间:2014.6.19
  • 页码:232-245
  • 分类:TF311.5[冶金工程—冶金机械及自动化]
  • 作者机构:[1]Guangxi Key Laboratory of Trusted Software, Guilin University of Electronic Technology, Guilin 541004, China
  • 相关基金:Supported by the National Natural Science Foundation of China (Nos. 61063002, 61100186, 61262008), Guangxi Natural Science Foundation of China (2011GXNSFA- 018164, 2011GXNSFA018166, 2012GXNSFAA053220), and the Key Project of Education Department of Guangxi.
  • 相关项目:面向信息流完整性的量化评估模型与技术研究
中文摘要:

As a complementary technology to Binary Decision Diagram-based(BDD-based) symbolic model checking, the verification techniques on Boolean satisfiability problem have gained an increasing wide of applications over the last few decades, which brings a dramatic improvement for automatic verification. In this paper, we firstly introduce the theory about the Boolean satisfiability verification, including the description on the problem of Boolean satisfiability verification, Davis-Putnam-Logemann-Loveland(DPLL) based complete verification algorithm, and all kinds of solvers generated and the logic languages used by those solvers. Moreover, we formulate a large number optimizations of technique revolutions based on Boolean SATisfiability(SAT) and Satisfiability Modulo Theories(SMT) solving in detail, including incomplete methods such as bounded model checking, and other methods for concurrent programs model checking. Finally, we point out the major challenge pervasively in industrial practice and prospect directions for future research in the field of formal verification.

英文摘要:

As a complementary technology to Binary Decision Diagram-based (BDD-basea) symDonc model checking, the verification techniques on Boolean satisfiability problem have gained an increasing wide of applications over the last few decades, which brings a dramatic improvement for automatic verification. In this paper, we firstly introduce the theory about the Boolean satisfiability verification, including the description on the problem of Boolean satisfiability verification, Davis-Putnam-Loge- mann-Loveland (DPLL) based complete verification algorithm, and all kinds of solvers generated and the logic languages used by those solvers. Moreover, we formulate a large number optimizations of technique revolutions based on Boolean SATisfiability (SAT) and Satisfiability Modulo Theories (SMT) solving in detail, including incomplete methods such as bounded model checking, and other methods for concurrent programs model checking. Finally, we point out the major challenge pervasively in indus- trial practice and prospect directions for future research in the field of formal verification.

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期刊信息
  • 《电子科学学刊:英文版》
  • 主管单位:中国科学院
  • 主办单位:中国科学院电子学研究所
  • 主编:朱敏慧
  • 地址:北京2702信箱
  • 邮编:100080
  • 邮箱:jc@mail.ie.ac.cn
  • 电话:010-62551772
  • 国际标准刊号:ISSN:0217-9822
  • 国内统一刊号:ISSN:11-2003/TN
  • 邮发代号:
  • 获奖情况:
  • 国内外数据库收录:
  • 俄罗斯文摘杂志,荷兰文摘与引文数据库,英国科学文摘数据库
  • 被引量:73