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中文摘要：
在高速有限冲击响应（Finite Impulse Response,FIR）数字滤波器的设计中,随着滤波器阶数的增加,保持数据流速率和有效使用硬件资源成为设计的一个重点和难点.基于高速并行有限冲击响应数字滤波器的基本原理,提出了一种将位平面法、正则有符号系数（Canonical-Signed Digit,CSD）编码算法和抽取算法应用于并行有限冲击响应数字滤波器的改进方法.设计通过Matlab仿真,在Quartus Ⅱ中编译、仿真、综合后下载到现场可编程门阵列（Field Programmable Gate Array,FPGA）中进行测试,结果显示,这种改进方法较好地解决了滤波器阶数和数据流速率与硬件资源之间的关系.
英文摘要：
With steady theoretical and technological development of digital signal processing, digital devices are rapidly replacing some analog devices due to their portability and highly reliable designs/ implementations. In radio astronomy digital-processing techniques have been increasingly applied in receivers, and have become important parts of receivers. The design of an FIR digital filter is critical in implementing digital techniques. In digital-processing modules for signals in radio-astronomy observation Analog-to-Digital Converters of operating frequencies at a few GHz are usually used. At so high frequencies high-rate data flows can form bottlenecks in data-storage processes. To avoid bottlenecks the hardware design of a digital filter needs to limit the data speed or to create diversions of data flows. The operating speed of a conventional filter is too slow though. Distributed Arithmetic （DA） algorithms have been proposed to improve speeds of conventional filters, but it is very difficult to achieve the optimal balance between the operating speed and the required resource of logic units in a conventional filter. As a result a conventional filter generally takes a large fraction of the chip area and uses a large amount of logic units. An FIR filter based on the Reduced Adder Graph algorithm can reduce the needed resources of logic units, but is slower than an improved DA filter. The issue of achieving a balance between data-rate performance and hardware-resource requirement becomes increasingly important and yet also increasingly difficult in designing high-speed FIR digital filters, as filters tend to have more taps. In this paper we present a new design of a parallel FIR digital filter by using the basic theory of high-speed parallel FIR digital filters, the bit-plane construction method, the CSD coding technique, and a signal-extraction algorithm. After having been simulated in the Matlab, the design was complied, simulated, and synthesized in the Quartus II; it was finally loaded into an FPGA device fo
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