中文摘要：

提供了一种适宜于多通道集成的低功耗、小面积14位125 MSPS流水线模数转换器（ADC）。该ADC基于开关电容流水线ADC结构,采用无前端采样保持放大器、4.5位第一级子级电路、电容逐级缩减和电流模串行输出技术设计并实现。各级流水线子级电路中所用运算放大器使用改进的“米勒”补偿技术,在不增加电流的条件下实现了更大带宽,进一步降低了静态功耗;采用1.75 Gbps串行数据发送器,数据输出接口减少到2个。该ADC电路采用0.18μm 1P5M 1.8 V CMOS工艺实现,测试结果表明,该ADC电路在全速采样条件下对于10.1 MHz的输入信号得到的SNR为72.5 d BFS,SFDR为83.1 d B,功耗为241 m W,面积为1.3 mm×4 mm。

英文摘要：

A low power, small die size 14-bit 125 MSPS pipelined ADC is presented. Switched capacitor pipelined ADC architecture is chosen for the 14-bit ADC. In order to achieve low power and compact die size, the sample and hold amplifier is removed, the 4.5-bit sub-stage circuit is used in the first pipelined stage. The capacitor down scaling technique is introduced, and the current mode serial transmitter is used. A modified miller compensation technique is used in the operation amplifiers in the pipelined sub-stage circuits, which offers a large bandwidth without additional current consumption. A 1.75 Gbps transmitter is introduced to drive the digital output code, which only needs 2 output pins. The ADC is fabricated in O. 18 μm 1.8 V 1P5M CMOS technology. The test resuhs show that the 14-bit 125 MSPS ADC achieves the SNR of 72.5 dBFS and SFDR of 83. 1 dB, with 10. 1 MHz input at full sampling speed, while consumes the power consumption of 241 mW and occupies an area of 1.3 mm × 4 mm.