中文摘要：

介绍了一种采用0.18μm 1P6M 1.8 V CMOS工艺的14 bit 250 MS/s电荷域流水线模数转换器（ADC）的全定制版图设计。为提高ADC性能,设计了一种基于标准CMOS工艺、适用于高速高精度电荷域流水线ADC的版图布局方式。版图实现过程中还综合使用了分布式的电源、地线、时钟网络拓扑结构。测试结果表明,该ADC电路在全速采样条件下对于20.1 MHz的输入信号得到的信噪比（SNR）为69.9 d BFS,功耗为230 m W。芯片面积为2.6 mm×4 mm,版图设计较好地实现了ADC电路性能。

英文摘要：

The full-custom layout design of a 14 bit 250 MS / s charge domain pipelined analog-to-digital converter（ ADC） was introduced with 0. 18 μm 1P6 M 1. 8 V CMOS process. In order to improve the performance of the ADC,a new floor planning method fitting for the high-speed high-precision charge domain pipelined ADC based on standard CMOS process was designed. Furthermore,the distributed power,ground wire and clock network topology structure were used in the implementation process of layout. The test results show that this new ADC circuit receives a 69. 9 d BFS signal noise ratio（ SNR） with 20. 1 MHz input signal at fullspeed sampling condition,while the power consumption is 230 m W and the area of the chip is 2. 6 mm ×4 mm. The layout design successfully realizes the performances of ADC circuits.