中文摘要：

在FPGAX-程设计中，经常需要用到大量的数据，由于FPGA片内存储器资源有限，一般利用SOPC开发的方法将数据烧写入Flash中，然后从Flash中读取数据进行处理。然而，读取Flash的时钟频率与处理模块的时钟频率往往不同，对这个问题进行了研究，采用FIFO的方法读取数据，增强了设计的性能和灵活性，并提出使用两个进程使读写同时进行，从而提高了读写的速度，更好的实现了系统的实时性。

英文摘要：

In design of FPGA projects, it often need plenty of data. Due to the resouse of on-chip memory is limited, it often use SOPC technology to put the data into flash, then read the data out from it. But the frequency between Flash and disposing module usually difference. In order to solve this problem, making use of FIFO in reading data is proposed. The performance and flexibility of the design is enhanced. Besides, it adopts two courses for reading and writing simultaneously, consequently, the speed is improved and the goal of real time better is obtained.