中文摘要：

设计了一种高性能、低功耗的Radix-8时序复数除法器.该复数除法器采用了逐位递归算法和操作数预变换技术,并在传统结构的基础上,选用冗余形式保留预校正变量,节省了超长进位加法器的使用,缩短了关键路径的延时.设计还通过实部和虚部商位的合并以及基于6输入查找表结构的硬件优化,提高了乘加逻辑单元的资源利用率.Stratix-II型现场可编程逻辑器件仿真验证表明,与使用超长进位加法器的传统结构相比,所设计的复数除法器的速度提高了44%,硬件资源减少了31%.

英文摘要：

A Radix-8 complex divider with high performance and low power is designed. The complex divider architecture adopts the digit-recurrence algorithm and the prescaling technique of operands, and has an optimizing function, with which the prescaled operands are kept in redundant forms so that long carry propagation adders are saved. Moreover, combination of the real and imaginary parts of the internal quotient digits and optimization for hardware mapping based on the 6-input look-up table are made to improve the utilization of logic resources. The proposed design is then implemented on Stratix-Ⅱ field programmable gate array. Simulation results and comparisons with the traditional structure show that the speed of the complex divider is increased by 44% and its hardware resources are reduced by 31%.