中文摘要：

为了缩短硅通孔的测试时间，针对符合JESD229和IEEEll49．1边界扫描协议的“存储＋逻辑”3D集成电路，提出一种硅通孔可测试性设计．首先在逻辑晶片上增加控制模块，用于控制存储晶片的边界扫描链；然后通过修改逻辑晶片上原有边界扫描链结构，实现串联和并联2种与存储晶片边界扫描链连接的模式；最后在逻辑晶片上增加寄存器，以保存测试过程所使用的配置比特，控制整体测试流程．实验数据表明，该设计仅比原有的IEEEll49．1边界扫描电路增加了0．4％的面积开销，而测试时间缩短为已有工作的1／6．

英文摘要：

logic die. Then, by transforming the boundary scan chains on the logic die, two connection modes, serial and parallel, are implemented. Finally, extra registers are added in the logic die to store TSV testing configuration bits. Experimental results show that, 0.4% area overhead is induced to the IEEE1149.1 boundary scan circuit, and TSV test time is reduced by 6X in comparison with the previous work.