在数字语音通信的声码器设计中,针对体系结构优化、指令集生成等问题,提出了一种基于算子的ASIP声码器设计方式,对其设计关键技术进行了讨论,并通过一个基于SELP算法的声码器设计实例与仿真结果加以验证,该声码器在20MHz主频下完成0.6kbps的SELP算法的平均功耗为200mw,完成编解码的运算复杂度为12.5MIPS.
In the design of vocoder for digital speech communication, ASIP (application specific instruction set processor) methodology is adopted which can satisfy the functionality and performance requirements. An operator-based ASIP vocoder design is proposed and the key techniques are discussed in detail, which is the solution for architecture optimization and methodology. One target application of ASIP vocoder implemented instruction generation of ASIP SELP algorithm is presented and simulation results indicate that the average consumption is 200 mW under the main frequency 20 MHz when it implements the 0.6 kbDs SELP algorithm,and its operation complexity is 12.5 MIPS.