中文摘要：

CRC是一种能发现并纠正信息在存储和传输过程中连续出现的多位错误的校验编码.分析CRC码的校验原理及特点,推导相邻字节间的CRC-32校验码的计算方法,利用组合逻辑并行快速计算当前字节的32位CRC校验码,使用Verilog HDL设计编码电路,通过FPGA实现CRC-32编码及检错功能.电路不仅可以计算任意长度的字节信息流的CRC-32校验码,还可嵌入到通信传输系统中快速并行实现CRC-32的编码及检错运算,保证信息正确可靠地传输.

英文摘要：

CRC is a check coding method to detect and correct continuous multiple error bits in the process of storage and transmission. In this paper, the principles and characteristics of CRC-32 are analyzed, the algorithms of CRC-32 between adjacent bytes are derived, the CRC-32 code of the current byte is fast calculated by combinational logic circuits in parallel, and this CRC-32 coding and error detection circuit coded in Verilog HDL is implemented in FPGA. In this circuit, the CRC-32 check code for byte stream with an arbitrary length is calculated, and it also can be embedded in communication transmission systems for error detection and correction to ensure that the information is transmitted accurately and reliably.