中文摘要：

本文分析了传统MEMS电容式加速度计模型的不足,根据三明治结构电容式加速度计的特点,考虑了寄生电容和热机械噪声的影响,建立了用Verilog-A硬件描述语言实现的模型。该模型与主流集成电路设计环境相兼容,具有很强的可移植性。模拟验证结果表明,该模型如实反映了MEMS电容式加速度计的工作状态,能够为设计单片集成的微弱电容检测电路提供有效的帮助。

英文摘要：

A new simulation model for sandwich capacitive accelerometers is proposed. Stray capacitance and thermo-mechanical noise is taken into account of the model which is implemented in Verilog-A HDL. This model is portable and compatible with the modern IC design environments. Simulation results show that it provides an effective approach for the design of monolithic capacitive sensor interfaces.