中文摘要：

针对面向雷达应用可重构系统中数据访存冲突严重、访存效率低等问题，设计了一种片上层次化缓存结构，并提出基于多存储体的线性步长可变的数据管理机制，通过建立计算阵列与各个存储体之间可配置的逻辑映射关系，有效降低了多个计算阵列并行工作时产生的访存冲突，提高了计算阵列的数据吞吐率，从而提高了可重构系统的数据访存性能．结果表明，该方案在有效控制硬件开销的同时，极大地提升了可重构系统的数据访存性能，以256～64×2^-10快速傅里叶变换为例，与经典并行缓存机制相比，可重构系统的数据访存性能提升了26．09％～54．60％．

英文摘要：

Aiming at the serious problems of access conflicts and low access efficiency, this paper proposes a hierarchical memory structure and data management strategy based on linear varying step-size for radar sub-algorithms. By establishing the logical mapping strategy between the reconfigurable arrays and the multi-bank memory, our design successfully reduces the access conflicts when the tasks assigned on differ- ent arrays fetch the required data in parallel and achieves a higher throughput. Consequently, the data ac- cess performance of the reconfigurable system is improved. Based on the TSMC 45 nm complementary met- al oxide semiconductor （CMOS） technology, the memory access performance can be increased highly for radar sub-algorithms. An example of the 256-point to 64 × 21-10-point fast Fourier transform （FFT） shows that the performance of the reconfigurable system compared to the representative parallel memory architec- ture （PMA） approach can be improved by 26.09% to 54.60%.