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Zero skew clock routing in X-architecture based on improved greedy matching algorithm
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相关项目:极大规模集成电路片上供电网络仿真及优化
同期刊论文项目
极大规模集成电路片上供电网络仿真及优化
期刊论文 19
会议论文 25
同项目期刊论文
Congestion-driven Multilevel Full-chip Routing Framework
Incremental Placement Based Clock Network Minimization Methodology,
基于线网分类的模拟电路自动布线器
考虑性能优化的冗余金属填充算法
同时考虑通孔电阻和耦合电容的时延驱动的层分配算法
Low power gated clock tree driven placement
Early Stage Power Supply Planning : A Heuristic Method for Codesign of P/G Network and Floorplan
Thermal aware placement in 3D ICs using quadratic uniformity modeling approach
ECP and CMP Aware Detailed Routing Algorithms for DFM
Random Walk Based Optimization Approach for Power/Ground Network
Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage,
Dummy Fill Aware Buffer Insertion After Layer Assignment Based On An Effective Estimation Model
Application of Optical Proximity Correction Technology
A MTCMOS Technology for Low-Power Physical Design
Floorplanning Considering IR-Drop for Voltage Island Design
Optimization of via distribution and stacked via in multi-layered P/G networks
采用统一建模的拥挤度驱动三维芯片布局算法
考虑通孔电阻和耦合电容的时延驱动的层分配算法