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中文摘要：
三维芯片设计对于提高芯片性能以及减少线长显现了很好的优势，降低连线拥挤度是保证布线成功率和三维芯片实现的关键．为了解决三维芯片布局阶段的拥挤度问题，提出一种拥挤度驱动的三维芯片布局算法．该算法首先对拥挤度单元分布和线长等优化目标进行统一建模，利用二次规划求解单元位置，得到一个单元分布均匀、走线均匀以及线长优化的总体布局；然后利用拥挤度驱动的层分配算法将空间上均匀分布的单元分配到各个芯片层上；最后对各个芯片层进行详细布局，消除重叠，优化拥挤度和线长．实验结果表明，该算法能够改善走线拥挤度约15％，而线长仅有3％的增加．
英文摘要：
The recent popularity of three dimensional （3D） IC technology stems from its enhanced performance capabilities and reduced wiring length. To improve the routahility and performance of 3D IC design, we develop placement algorithm to reduce congestions of 3D circuit design. Our algorithm consists of three phases. Firstly, in global placement phase, we use quadratic uniformity modeling approach to integrate congestion, cell distribution and wirelength optimization into one quadratic function, and utilize quadratic programming to solve the function to get the position of cells in 3D space. Secondly, we propose congestion aware layer assignment algorithm to assign the cell into different layers. Finally, detailed placement is employed to remove overlaps, optimize wirelength and reduce congestion in each layer. Experimental results show that our algorithm is efficient with 15% congestion reduction and only 3% wirelength increase.
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