中文摘要：

分析了一个应用于测量的16位精度开关电容Δ-Σ模数调制器.该调制器采用3阶1位单环包含局部谐振器的前馈结构,在保证其具有较大的输入信号允许范围的同时引入零点优化来提高信号/噪声失真比.整体电路使用TSMC 0.35μm混合信号CMOS工艺,采用Spectre进行仿真.结果表明,在信号输入带宽为1 kHz、超采样率128条件下,调制器的动态输入范围为102 dB;在信号为-3.5 dB满幅输入时,其最大信号/噪声失真比为97.84 dB.此外,在1.5 V供电电压下,调制器的功耗仅为88μW,表现出较好的低功耗高精度性能.

英文摘要：

A 16 bit switched-capacitor （SC） delta-sigma （△-∑） analog to digital （AD） modulator is proposed to meet the high resolution low speed demands of AD conversion for measurement applications. A 1 hit quantizer and single path 3-order feed-forward topology with local resonator is employed in the modulator. The architecture allows increasing input amplitude and the introduced zero optimization results in higher maximum SNDR. The simulation using Spectre is based on the TSMC 0.35 μm mixed signal CMOS process. The results show the modulator achieves a simulated dynamic-range （DR） of 102-dB and a peak signal-to-noise-and-distortion-ratio （SNDR） of 97.84 -dB @ - 3.5 dB FS in a 1-kHz signal bandwidth with an oversampling ratio（OSR） of 128. The power dissipation of the modulator is only 88-μW under 1.5-V supply voltage, indicating low power and high resolution.