为了兼顾模拟集成电路设计优化的求解精度和计算效率,提出一种基于正项式模型修正技术的几何规划优化方法.首先将模拟集成电路的设计目标与约束简化为正项式模型,然后在采用几何规划方法迭代优化的过程中利用晶体管级SPICE仿真不断修正这一正项式模型.实例表明,与传统基于公式的优化方法和基于仿真的优化方法相比,该方法能够在尽量保证计算效率和全局最优解的前提下使优化精度满足晶体管级SPICE仿真的要求.
This paper proposes a geometric programming method combined with model revision technique for optimizing the design parameters of analog integrated circuits. Applying this method, the design objective and constraints are formulated as posynomial model of the design parameters firstly. Then, geometric programming is iteratively utilized to optimize the device size, during which transistor-level SPICE simulations are employed to continually revise the posynomial model. An example of a widely used operational amplifier circuit is applied to demonstrate that the proposed method could achieve the SPICE-level accuracy without sacrificing too much efficiency when compared to the existing equation-based methods and simulation-based approaches.