提出了一种固定码长的多码率多边LDPC码译码器,该译码器采用对校验比特信息进行间隔删余的算法实现其多码率译码,并设计了一种适合多码率多边LDPC码的部分并行译码结构。基于该结构在FPGA平台上实现了码长为640bit,码率为0.5~0.8的多边LDPC码译码器。
A multi-rate Multi-edge Type LDPC (MET-LDPC) decoder is presented by puncturing the parity bits every one bit, and a suitable multi-rate MET-LDPC code partial parallel decoding structure is designed. FPGA platform uses this structure to achieve the multi-rate MET-LDPC decoder with code-length 640 bit and the code rate range from 0.5 to 0.8.