中文摘要：

提出了一种Crossbar总线与共享总线相结合的SoC系统级通信综合方法．从实际应用的系统级设计出发，根据待互连处理单元和存储单元之间的通信量，综合出Crossbar总线与共享总线相结合的总线拓扑结构．采用遗传算法，以实际应用的通信延迟为约束，考虑总线竞争、通信同步带来的通信延迟，综合出满足延迟约束的总线参数．对综合后的Crossbar总线与共享总线进行事务级建模和分析，进一步优化生成的总线拓扑结构．实验证明，该方法解决的问题较以往更加全面，生成的总线拓扑结构和参数更优．

英文摘要：

The on-chip communication architecture is a fabric that integrates the various SoC（system- on-chip） components, and provides them with a mechanism for the exchange of data. It has a significant impact on SoC performance. The bus based communication architectures are the most popular communication styles up to now. There are mainly two kinds of bus topologies, shared bus topology and crossbar bus topology. There is a great deal of research in the field of system level communication synthesis, but previous bus based communication synthesis research is confined to shared bus synthesis or crossbar bus synthesis. Few works take both shared bus and crossbar bus into account. In this paper, a novel system-level communication synthesis methodology containing crossbar bus and shared bus is presented. Starting with the communication traffic between the system-level processing elements and storage units, the proposed methodology synthesizes an optimal bus topology containing crossbar bus and shared bus. It uses a genetic algorithm to synthesize bus parameters which satisfy the communication delay constraints while considering bus contention and communication synchronization. It models the generated crossbar bus and shared bus at transaction level and optimizes the communication architectures. Experiments show that the proposed methodology results in about 10% component savings when compared with the methodology ever before.