中文摘要：

IP（intellectualproperty）核复用的设计思想使得SoC（system—on—a—chip）成为当今集成电路设计的主流，但对其进行测试变得异常困难，这就是需要为SoC设计测试结构的主要原因。传统的测试结构功能是：根据自动测试设备（automatictestequip—mcnt，ATE）提供的某一频率，将测试数据通过测试结构依次施加到SoC内部的IP核，并获取测试响应传输到ATE中，以分析其功能正常与否。但是这种测试结构存在很多缺点，其中最主要的是未考虑测试设备提供的测试访问机制（testaccessmecha—nism，TAM）的宽度与SoC内各IP核的最佳测试带宽是否一致。对这一系列问题进行研究，提出一种基于带宽匹配思想的SoC测试结构设计方法，该方法主要通过一个带宽匹配转换模块，实现测试数据的宽度调整和施加频率的调整，在牺牲了芯片部分额外面积的前提下，很好地实现了测试带宽和测试频率的匹配，缩短了SoC的测试时间。最后将这种方法应用在ITC’02标准测试集上，实验结果验证了该方法的有效性。

英文摘要：

The reuse of intellectual property （IP） cores reduces the design cycle of systemonachip （ SoC）, which is the main stream technology in modern integrated circuit （IC） design. The test architecture is emerged because test data can not be transferred to IPs directly through SoC pins. Traditional test architecture works at a frequency provid ed by automatic test equipment （ATE）. The procedure of testing an IP core is ： shifting in a test stimulus to the IP core scan chain, launching the test in one capture cycle, and shifting the test response out while shifting in the next test stimulus. However, this architecture has many shortcomings, such as the number of ATE channels does not match the best bandwidth to test the IPs in SoC. Therefore, a test architecture based on bandwidth matching is pro posed in this paper, in which a bandwidth matching module is used to adjust the width and frequency of the test da ta, and to shorten the test time, which requires extra test area though. Experiment results on ITC＇02 benchmark show the availability of the proposed method.