提出一种联合构造规则低密度校验(LDPC)码的方案.通过该方法构造的规则LDPC码不仅具有良好的纠错性能,而且适合于采用部分并行结构的译码器来实现高速译码,从而使得所构造的LDPC码在硬件复杂度与译码吞吐量之间具有较好的折衷.该译码器可兼容多种码长、多种码率的LDPC码,因此只需要设计一个译码器,就可以完成对具有相同列重的不同LDPC码的译码.
This paper presented a joint design approach to construct a class of regular low-density parity- check (LDPC) codes with both good error-correct performance and high-speed partly parallel decoder, which means more flexible tradeoffs between decoder hardware complexity and decoding speed. Moreover, this decoder is also compatible with various block lengths and code-rates, so only one decoder is needed for different LDPC codes with the same column weight.