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中文摘要：
针对H．264／AVC中的去块效应滤波器，该文提出了一种新的滤波处理顺序，能够显著减小片上数据缓存容量，并以此为基础设计了一种去块效应滤波器的VLSI硬件新结构。该结构利用数据复用机制减少对片外存储的访问量、节省处理时间，同时不使用片内SRAM，将对片内SRAM的访问降为0。仿真结果显示，该电路在工作频率为100MHz时对HDTV能较好地实现实时滤波；在0．18μm工艺下，综合后的等效逻辑门数只有16．8k。
英文摘要：
A new VLSI architecture of deblocking filter is developed for H.264/AVC system. In the presented architecture, a novel filter scheduling is proposed to reduce the size of local data buffer, and an enhanced data reuse technology is adopted to reduce the number of external memory access, thus the speed of filtering process is significantly improved as well. What＇s more, this architecture employs no on-chip SRAM, so there is no on-chip SRAM access. Simulation results show that the new filter can support real-time deblocking for HDTV video application when it works at 100 MHz. The synthesized logic gate count is only 16.8k with 0.18μm CMOS technology.
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