中文摘要：

为提高电路的调试性并降低逻辑资源消耗, 提出-种用于硬件模拟平台的扫描链插入方法, 利用FPGA 中未被完全使用的逻辑资源实现了扫描逻辑. 首先在网表中找出所有连接到D 触发器输入端的部分使用查找表; 然后采用逻辑混合的方法修改查找表内容和引脚连接, 将D 触发器改为扫描触发器; 最后将所有扫描触发器前后相连,构建扫描链. 该方法工作在网表级, 与现有FPGA 开发流程兼容, 便于与现有工具集成. 对15 个不同规模ITC’99 基准电路进行实验的结果表明, 该方法可平均减小22.9%的逻辑资源消耗.

英文摘要：

To improve circuit debuggability and reduce logic resource usage, this paper proposes an approach for scan chain insertion in hardware emulation platform, which exploits partially used look-up tables (LUTs) on FPGAs to realize the extra logic required by the scan chain. The approach firstly finds all partially used LUTs which are connected to the inputs of D flip-flops in a netlist. Secondly, the contents of the found LUTs are changed to accommodate the extra logic, in order to convert the D flip-flops to scan flip-flops. Finally, all scan flip-flops are connected to form the scan chain. The whole approach is automated and can be easily integrated in-to the current FPGA development flows. The experimental results on ITC’99 benchmark circuits show that the proposed approach can effectively reduce logic resource usage by 22.9% on average.