中文摘要：

根据基2分解的FFT算法理论,采用了流水线与并行结合的方式,设计了一种基于FPGA芯片的FFT计算模块.该模块由地址控制单元和存储单元配合蝶形运算单元,实现了计算长度为1 024点、数据类型为32位浮点型的FFT计算.测试结果表明,该模块在CycloneIII芯片中耗用3 928个LE和123kb的存储器资源,稳定工作频率可达110 MHz,完成1 024点FFT变换时间为95.66μs,具有良好的运算性能.

英文摘要：

With the reference of radix-2 decimation fast fourier transform（FFT） theory, we design a FFT module based on field programmable gate array（FPGA） which gets a structure combined pipeline with par- allel algorithm. The module con has a length of 1 024 and 32-bit FFT module consumes 3 928 of tains address control and storing control cooperati float-point data type. The test with verification LE and 123kb of Ram. The maximum working Thus a 1 024-point-FFT consumes only 95.66μs. The conclusion is that the rood performance. ng with butterfly unit. It shows that the designed frequency is 110 MHz. ule gets good operational