中文摘要：

本论文提出了一种双模可配置Delta-Sigma（ΔΣ）调制器,该调制器可配置为两种结构：适用于低频高精度应用的3阶4比特量化的结构和适用于高频低精度应用的2阶4比特量化的结构.调制器在两种模式下复用了包括开关和电容在内的绝大部分电路模块,并采用了一种高效的运算放大器（OTA）结构和带有输入失调校准技术（IOS）的比较器结构,此外还引入了动态元件匹配（DEM）电路来减小电容失配的影响.本设计使用的是0.18μm的CMOS工艺,调制器在两种模式下分别可以达到77.1dB和108.9dB的峰值信号谐波失真比（SNDR）,对应的输入信号带宽分别为1.25 MHz和39kHz,芯片的整体功耗为12mW.

英文摘要：

This paper presents a dual-mode delta-sigma （ΔΣ） modulator. The modulator can be configured for two structures, 3rd-order 4-bit in low-frequency high-resolution applications, and 2nd-order 4-bit in high-frequency low- resolution applications. Most of the circuit parts including the capacitors and switches are shared in both modes. An efficient OTA and comparators with Input Offset Calibration （IOS） technique are adopted. The modulator is fabricated in 0. 18 μm CMOS technology. It achieves 77. 1 dE, and 108. 9 dB peak signal-to-noise and distortion ratio （SNDR） separately in two modes with 39 kHz and 1.25 MHz input signal bandwidth. The power consumption is about 12 mW.