中文摘要：

为有效降低实际应用中多通道低频正余弦信号以及高频正余弦信号的DPSD检测算法对DSP处理能力的过高要求，分析了数字信号处理硬件一般架构，提出基于现场可编程门阵列（FPGA）的DPSD算法实现的2种有效架构。针对多通道检测，该架构能够显著降低硬件资源消耗；针对高频检测，架构最大可实现采样率为系统时钟。该结构在FPGAA3P400实现最大70Mbit／s的采样率，能够极大地降低DSP在高采样率时DPSD的计算负担。讨论了设计思路与方法以及新设计在FPGA中的实现，给出详细的硬件结构、有限状态机（FSM）图、FPGA硬件资源消耗以及仿真测试结果。这2种基于FPGA的DPSD架构具有灵活的可配置性，在保证计算精度的同时，可满足不同的通道数量以及速率检测需求。

英文摘要：

Introduced are the practical applications of digital phase sensitive detector （DPSD）. In order to effectively reduce the excessive demands of the practical application of the multi-channel low-frequency sine and cosine signal and high-frequency sine and cosine signal DPSD detection algorithms on the DSP processing capability, proposed is a DPSD algorithm based on the Field Programmable Gate Array （FPGA） to achieve two effective frameworks respectively by analyzing the general architecture of digital signal processing hardware. For multi-channel detection, the architecture is able to reduce hardware resource consumption significantly. For the high- frequency detection, the maximum sampling rate of the system clock can be achieved. The structure mapped in FPGA A3P400 may reach 70 Mbit/s sampling rate, so the structure will greatly reduce the computational burden of the DSP in the high sampling rate DPSD. Detailed design ideas and methods as well as new designs in the FPGA implementation are discussed, the hardware structure, FSM state machine diagram and FPGA hardware resource consumption and simulation test results are shown. These two methods based on the FPGA DPSD architecture are flexible and configurable to meet the different number of channels and sampling rate requirements while ensuring the calculation accuracy.