中文摘要：

为降低实现高阶矩阵SVD时的硬件复杂度和计算延时,本文改进了CORDIC迭代结构,设计了一种用于SVD的低硬件复杂度、高速CORDIC计算单元.本文以2x2矩阵为例,基于Xilinx Virtex6硬件平台设计并实现了使用优化后CORDIC计算单元的SVD模块,在19bit位宽下吞吐率达25.9Gbps.对比Xilinx IP core中同类模块,本文设计节省27.6%寄存器,27.7%查找表,实时性提高14%.对高阶矩阵,本文给出资源消耗趋势曲线,可证明优化后CORDIC计算单元能降低16阶矩阵SVD模块约40%的硬件复杂度.

英文摘要：

In order to reduce the hardware complexity and the delay of high-order SVD processor, two improved CORDIC modules including Arc Tan and Rotation functions are designed. These two improved CORDIC modules have better performance in terms of register saving and real-time quality. In this paper, a 2x2SVD module using above-mentioned CORDIC modules with 19bit data width has implemented on XilinxVirtex6 and the throughout reaches 25.9Gbps. Compared with the 2x2SVD module using IP core, it reduced 27.6 % registers, 27.7 % LUTs and improved 14 % real-time performance. Moreover, the trend curves of hardware consumption are presented which have testified that these two improved CORDIC modules can reduce 40% hardware complexity of 16-order SVD processor.