中文摘要：

设计并实现了一种采用电感电容振荡器的电荷泵锁相环,分析了锁相环中鉴频/鉴相器（PFD）、电荷泵（CP）、环路滤波器（LP）、电感电容压控振荡器（VCO）的电路结构和设计考虑。锁相环芯片采用0.13μm MS＆RF CMOS工艺制造。测试结果表明,锁相环锁定的频率为5.6～6.9 GHz。在6.25 GHz时,参考杂散为-51.57 dBc;1 MHz频偏处相位噪声为-98.35 dBc/Hz;10 MHz频偏处相位噪声为-120.3 dBc/Hz;在1.2 V/3.3 V电源电压下,锁相环的功耗为51.6 mW。芯片总面积为1.334 mm2。

英文摘要：

A charge pump phase locked loop（PLL） with LC voltage controlled oscillator（VCO） was presented.The circuit structures of the frequency/phase detector,charge pump,loop filter and LC VCO were analyzed and the design consideration was given.The chip was fabricated in 0.13 μm MS RF CMOS technology.The test results show that the PLL operates at 5.6-6.9 GHz,and the phase noise of -98.35 dBc/Hz at 1 MHz offset and -120.3 dBc/Hz at 10 MHz offset is achieved.When the frequency is 6.25 GHz,the reference spur is -51.57 dBc.The PLL chip occupies 1.334 mm2,exhibites a power consumption of 51.6 mW at 1.2 V/3.3 V power supply.