位置：成果数据库 > 会议 > 会议详情页
An efficient lightweight shared cache design for chip multiprocessors
  • 所属机构名称：清华大学
  • 会议名称：8th International Symposium on Advanced Parallel Processing Technologies, APPT 2009
  • 成果类型：会议
  • 相关项目：支持高速缓存一致的片上网络关键技术研究
作者： Wang, Jinglei|Wang, Dongsheng|Xue, Yibo|Wang, Haixia|
同会议论文项目
支持高速缓存一致的片上网络关键技术研究
期刊论文 75 会议论文 63 专利 12
同项目会议论文
A high effective indexing and retrieval method providing block-level timely recovery to any point-in
Improve clock gating through power-optimal enable function selection
Peak temperature control in thermal-aware behavioral synthesis through allocating the number of reso
A thermal-driven force-directed floorplanning algorithm for 3D ICs 1
HARDWARE OPTIMIZATIONS OF VARIABLE BLOCK SIZE HADAMARD TRANSFORM FOR H.264/AVC FREXT
FPGA implementation of variable-precision floating-point arithmetic
Coherent temporal streams in PARSEC
VPFPAP: A special-purpose VLIW processor for variable-precision floating-point arithmetic
Dynamic reusability-based replication with network address mapping in CMPs
Enhanced adaptive insertion policy for shared caches
Accurate and fast cell spreading for force directed placement
Fast placement for large-scale hierarchical FPGAs
A novel cache organization for tiled chip multiprocessor
Fast congestion-aware timing-driven placement for Island FPGA
Scalable proximity-aware cache replication in chip multiprocessors
ONE-ROUND RENORMALIZATION BASED 2-BIN/CYCLE H.264/AVC CABAC ENCODER
TIPO: A heuristic algorithm for delay constrained power optimization
Fast placement for large-scale hierarchical FPGAs
A novel cache organization for tiled chip multiprocessor
Fast congestion-aware timing-driven placement for Island FPGA
Network Caching for Chip Multiprocessors
A DyadicCluster method used for nonlinear placement
A new model of nonblocking multicast WDM optical switching network with reduced complexity
FPGA accelerating double/quad-double high precision floating-point applications for ExaScale computi
Behavioral level dual-Vth design for reduced leakage power with thermal awareness
Markov clustering based placement algorithm for island-style FPGAs
Cycle-Accurate 64+-Core FPGA-Based Hybrid Simulator
A two-phase differential synchronization algorithm for remote files
Fast hierarchical cache directory: A scalable cache organization for large-scale CMP
A reliable detail placement tool for mixed mode IE design
Storage device performance prediction with selective bagging classification and regression tree
A design of embedding rewiring into routing for FPGA improvement
Blocking LU decomposition for FPGAs
A cache replacement policy using adaptive insertion and re-reference prediction
A detailed router for hierarchical FPGAs based on simulated evolution
Wirelength optimization for multilevel hierachical FPGA
Power optimization through edge reduction in LUT-based FPGA technology mapping
FPGA accelerating three QR decomposition algorithms in the unified pipelined framework
Network Victim Cache: Leveraging Network-on-Chip for Managing Shared Caches in Chip Multiprocessors
A fine-grained pipelined implementation for large-scale matrix inversion on FPGA
Fast placement for large-scale hierarchical FPGAs
A novel cache organization for tiled chip multiprocessor
Fast congestion-aware timing-driven placement for Island FPGA
Network Caching for Chip Multiprocessors
An efficient lightweight shared cache design for chip multiprocessors
Implementation of rotation invariant multi-view face detection on FPGA
A fast routability-driven router for hierarchical FPGAs based on tabu search
Network Caching for Chip Multiprocessors
An efficient lightweight shared cache design for chip multiprocessors
Fast placement for large-scale hierarchical FPGAs
A novel cache organization for tiled chip multiprocessor
Fast congestion-aware timing-driven placement for Island FPGA
Network Caching for Chip Multiprocessors
An efficient lightweight shared cache design for chip multiprocessors
Wear-resistant hybrid cache architecture with phase change memory
Stochastic prefix-based fault tolerant source routing algorithm for network on chip
A timing-perspective study on the wire model in placement
High performance cache block replication using re-reference probability in CMPs
Special-purposed VLIW architecture for IEEE-754 quadruple precision elementary functions on FPGA
Proximity-aware cache Replication
Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization
A read-write aware replacement policy for phase change memory