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Compressing test data for deterministic BIST using a reconfigurable scan architecture
  • 所属机构名称：清华大学
  • 成果类型：会议
  • 相关项目：容错计算
同会议论文项目
容错计算
期刊论文 19 会议论文 17
同项目会议论文
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Design for scan testing with low test application cost and low test data volume by reconstructing sc
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Scan testing for complete coverage of path delay faults with reduced test data volume, test applicat
Fast and effective fault simulation for path delay faults based on selected testable paths