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容错计算
  • 项目名称：容错计算
  • 项目类别：国家杰出青年科学基金
  • 批准号：60425203
  • 申请代码：F020105
  • 项目来源：国家自然科学基金
  • 研究期限：2005-01-01-2008-12-31
  • 项目负责人：向东
  • 负责人职称：教授
  • 依托单位：清华大学
  • 批准年度：2004
中文摘要：

目前最流行的测试方法是扫描测试。扫描测试可将测试问题变为组合电路的测试问题，大大简化了测试码产生的代价及增加测试的故障覆盖率，因而可大大地提高测试的质量。扫描测试所带来的高测试代价，测试功耗及测试数据容量也是难以逾越的问题。本项目将提出一系列可测试性设计技术,其特点是测试代价低额外开销低, 测试功耗低, 且测试数据容量小。扫描测试的测试代价，测试功耗及测试数据的容量是非常严峻且急待解决的问题。本项目

中文主题词： 低功耗扫描测试; 测试时间;
成果综合统计
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  • 期刊论文
  • 会议论文
  • 专利
  • 获奖
  • 著作
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期刊论文
mesh网高效无死锁路由算法
Using weighted scan enable signals to improve test effectiveness of scan-based BIST
Partial path set-up for fault-tolerant routing in hypercube multicomputers
Low Power Scan testing using a two-stage scan architecture
Improving the effectiveness of scan-based BIST using scan chain partitioning
A reconfigurable scan architecture with weighted scan enable signals for deterministic BIST
Scan testing with low power, test application time and reduced test data volume
Test power reduction using clock disabling
Scan BIST with biased scan test signals
Reconfigured scan forest for test application cost, test data volume and test power reduction
Fault-tolerant routing and multicasting for hypercube multicomputers based on partial path set-up
Constraining transition propagation for low power scan testing using a two-stage scan architecture
Using weighted scan enable signals to improve the test effectiveness of scan-based BIST
低成本的两级扫描测试结构
不规则网络拓扑结构下的多棵树路由算法研究
无线自组网络中的基于多个支配集的路由协议
Mesh网中高效无死锁自适应路由算法
会议论文
Compressing test data for deterministic BIST using a reconfigurable scan architecture
Using weighted scan enable signals to improve test effectiveness of scan-based BIST
Conflict-driven scan architecture for high transition fault coverage and low power
Design for scan testing with low test application cost and low test data volume by reconstructing sc
New techniques for accelerating small delay ATPG and generating compact test sets
Deadlock-free adaptive routing in 2D tori with a new turn model
Generating compact robust and non-robust tests for complete coverage of path delay faults based on s
Deadlock-free adaptive routing in meshes based on cost-effective deadlock avoidance schemes
Deadlock-free fully adaptive routing in 2-dimensional tori based on a new virtual network partitioni
Deadlock-free fully adaptive routing in tori based on a new virtual network partitioning scheme
Pattern-directed circuit partitioning for test power reduction
A density adaptive routing protocol for large-scale Ad hoc networks
Fault-tolerant routing in meshes /tori using planarly constructed fault blocks
Scan-based BIST using an improved scan forest architecture
Localizing test power consumption for scan testing
Scan testing for complete coverage of path delay faults with reduced test data volume, test applicat
Fast and effective fault simulation for path delay faults based on selected testable paths
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