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An improved FPGA packing algorithm based on dual-output basic logic elements
  • 所属机构名称：武汉大学
  • 会议名称：IEEE 9th International Conference on ASIC (ASICON 2011)
  • 成果类型：会议
  • 相关项目：集成电路设计（包括ＣＡＤ）
作者： Gao Feng Wang|Xian Yang Jiang|Shilei Sun|Ying Liu|
同会议论文项目
集成电路设计（包括ＣＡＤ）
期刊论文 38 会议论文 20 专利 8
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