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An Efficient FPGA Packing Algorithm Based on Simple Dual-Output Basic Logic Elements
  • 所属机构名称：武汉大学
  • 会议名称：IEEE 8th International Conference on ASIC
  • 成果类型：会议
  • 会场：Changsha, PEOPLES R CHINA
  • 相关项目：集成电路设计（包括ＣＡＤ）
作者： Jiang, Xianyang|Sun, Shilei|Liu, Ying|Wang, Gaofeng|
同会议论文项目
集成电路设计（包括ＣＡＤ）
期刊论文 38 会议论文 20 专利 8
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