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中文摘要：
针对特定通信系统中需要实现快速、高精度的时间同步需求，设计了一种基于 FPGA 同步信号生成的系统方案。系统以C/A码码片为最小时间刻度，通过对信号中码片数计数输出秒脉冲信号，并在同源情况下，根据码相位累加器溢出后残余值的特点，调整秒脉冲信号的输出位置。结果表明，调整后的秒脉冲信号同步精度能达到纳秒级，在工程上具有一定的应用价值。
英文摘要：
To satisfy demands of the specific communication system on fast-high precision time synchronization,a scheme of synchronizing signal generated based on FPGA is designed.C/A code-chip is the minimum time calibration for this system, 1PPS signal is exported by computing chip number,and according to character of residual value produced by code phase ac-cumulator,the output location of second pulse signal is adj usted in the same clock source.Interrelated analyses show the synchronization error of second pulse can be controlled within nanosecond after adj ustment.This scheme is of certain refer-ence value to engineering application.
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