中文摘要：

<正>This paper presents the design and analysis of a high speed broadband divide-by-2 frequency divider. The proposed divider is a dynamic source-coupled logic(DSCL) structure formed with two dynamic-loading master-slave D latches,which enables high frequency operation and low power consumption.This divider exhibits a wide locking range from 7-27 GHz and the minimum power consumption is only 1.22 mW from a 1.2 V supply.The input sensitivity is as low as -25.4 dBm across the operating frequency range.This chip occupies 685×430μm~2 area with two on-chip spiral inductors in 90 nm CMOS process.

英文摘要：

This paper presents the design and analysis of a high speed broadband divide-by-2 frequency divider. The proposed divider is a dynamic source-coupled logic（DSCL） structure formed with two dynamic-loading master-slave D latches,which enables high frequency operation and low power consumption.This divider exhibits a wide locking range from 7-27 GHz and the minimum power consumption is only 1.22 mW from a 1.2 V supply.The input sensitivity is as low as -25.4 dBm across the operating frequency range.This chip occupies 685×430μm~2 area with two on-chip spiral inductors in 90 nm CMOS process.