中文摘要：

We present a 31–45.5 GHz injection-locked frequency divider(ILFD) implemented in a standard 90-nm CMOS process. To reduce parasitic capacitance and increase the operating frequency, an NMOS-only cross-coupled pair is adopted to provide negative resistance. Acting as an adjustable resistor, an NMOS transistor with a tunable gate bias voltage is connected to the differential output terminals for locking range extension. Measurements show that the designed ILFD can be fully functional in a wide locking range and provides a good figure-of-merit. Under a 1 V tunable bias voltage, the self-resonant frequency of the divider is 19.11 GHz and the maximum locking range is 37.7% at 38.5 GHz with an input power of 0 d Bm. The power consumption is 2.88 m W under a supply voltage of 1.2 V. The size of the chip including the pads is 0.62 mm×0.42 mm.

英文摘要：

We present a 31-45.5 GHz injection-locked frequency divider （ILFD） implemented in a standard 90-nm CMOS process. To reduce parasitic capacitance and increase the operating frequency, an NMOS-only cross-coupled pair is adopted to provide negative resistance. Acting as an adjustable resistor, an NMOS transistor with a tunable gate bias voltage is connected to the differential output terminals for locking range extension. Measurements show that the designed ILFD can be fully functional in a wide locking range and provides a good figure-of-merit. Under a 1V tunable bias voltage, the self-resonant frequency of the divider is 19.11 GHz and the maximum locking range is 37.7% at 38.5 GHz with an input power of 0 dBm. The power con- sumption is 2.88 mW under a supply voltage of 1.2 V. The size of the chip including the pads is 0.62 mm×0.42 mm.