中文摘要：

介绍了一种应用于宽带低相位噪声的频率综合器．此频率综合器为兼容DRM，DAB，AM和FM的射频前端提供本振信号．为了覆盖所有频段的信号，提出了一种新的频率规划和系统结构．此频率综合器包含宽带低功耗低相位噪声的VCO和高速宽带低功耗的大分频比吞吐脉冲分频器等模块．所设计的频率综合器应用中芯国际的0．18μm RF CMOS工艺进行了流片实现．整个芯片面积为1425μm ×795μm，包括测试驱动电路和焊盘．测试结果表明，压控振荡器振荡频率范围为2．27～3．57 GHz．在频偏为1 MHz时，其相位噪声为120．22 dBc/Hz；吐脉冲分频器的工作频率范围为0．9～3．4 GHz；在频偏为10 kHz时，锁相环内的相位噪声为-59．52 dBc/Hz，完全满足DRM/DAB/AM/FM射频前端的要求．此频率综合器在1．8 V的电源电压下，其功耗为47 mW（包括测试驱动的功耗）．

英文摘要：

This paper describes a wideband low phase noise frequency synthesizer.It operates in the multi-band including digital radio mondiale DRM digital audio broadcasting DAB amplitude modulation AM and frequency modulation FM .In order to cover the signals of the overall frequencies a novel frequency planning and a new structure are proposed. A wide-band low-phase-noise low-power voltage-control oscillator VCO and a high speed wide band high frequency division ratio pulse swallow frequency divider with a low power consumption are presented.The monolithic DRM/DAB/AM/FM frequency synthesizer chip is also fabricated in a SMIC＇s 0.18-μm CMOS process.The die area is 1 425 μm ×795 μm including the test buffer and pads. The measured results show that the VCO operating frequency range is from 2.22 to 3.57 GHz the measured phase noise of the VCO is 120.22 dBc/Hz at 1 MHz offset the pulse swallow frequency divider operation frequency is from 0.9 to 3.4 GHz.The phase noise in the phase-locked loop PLL is-59.52 dBc/Hz at 10 kHz offset and fits for the demand of the DRM/DAB/AM/FM RF front-end. The proposed frequency synthesizer consumes 47 mW including test buffer under a 1.8 V supply.