中文摘要：

根据高效三步法的特点，提出了有效的数据流和相应的VLSI结构。该数据流充分利用参考帧搜索点之间数据重叠的特征，以减少数据存储器访问的次数，从而减少了运动估计中功率消耗最大部分的操作。通过对各种测试序列的仿真证明，该VLSI结构有效地实现了高效三步法，适合MPEG-4和HDTV应用。

英文摘要：

An efficient data flow pattern and corresponding hardware architecture for efficient three step search （E3SS） algorithm are preseated for motion estimation. The data flow exploits the overlap of reference data among the search points to reduce data memory accesses that are the most power consuming operations in motion estimation. The corresponding hardware architecture imple- ments the search for two different patterns of E3SS efficiently. Simulation results show that the average number of cycles required to make a block matching for different test sequences is 280, which fulfills the speed requirement of MPEG-4 and HDTV standards.