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中文摘要：
一般比较器往往只能提供固定延迟时间的跳变信号，这样对后级执行电路产生很大的局限性。文章提出一种延迟时间可调的新型电压迟滞比较器设计,电路在1．5μm BCD（Bipolar-CMOS-DMOS）工艺下实现。该比较器的正跳变点电压为1．270V，迟滞电压为3mV，上升延迟时间为20μs，且可以根据需要方便地予以调节。该比较器最小分辨率为±0．1mV。具有结构简单、通用性好和功耗低的特点，可广泛应用于不同的SoC环境。
英文摘要：
Delay time is usually invariable in a usual eomparator, thus there will be a lot of limits for the following executive circuits, In this paper, a novel voltage hysteretic comparator with adjustable delay time is designed and simulated. This circuit can be realized in BCD（Bipalar-CMOS-DMOS） technology. The simulation results show that its positive switching point voltage is 1.270V with 3mV of hysteresis. The rising delay time is about 20μs and can be conveniently adjusted according to the requirements. The LSB of the comparator is ±0.1mV. The circuit is simple and easy to use. It is of low power. It can be widely applied to different SoC environments.
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