介绍了一种基于LVDS接口的PCM解码板的系统组成,重点说明了LVDS接口的各分层协议及基于FP-GA实现的PCM解码方法,讨论了LVDS总线以时钟和数据恢复技术解决限制数据传输速率的信号时钟参差问题。通过测试分析,该板在PCM解码的抗干扰能力及实现解码数据的高速、可靠传输方面均达到了系统提出的技术指标。
The PCM decoding system based on LVDS interface FPGA is designed.Emphasis is put on the definition of the LVDS bus protocol and design of the PCM decoding circuit.The clock recovered from data through the LVDS bus is discussed.This circuit is put into practice with the characteristics of stable work and better anti-interference ability