中文摘要：

为了提高芯核水印的嵌入容量和水印的安全性能，通过分析现有的基于FPGA的芯核水印技术，提出一种高容量的分散式FPGA芯核水印算法．算法设计首先采用一种水印预处理压缩机制，该机制主要是将加密后的版权信息构造成特定的线性组合表达式加以实现；其次，生成的线性组合表达式转换成水印嵌入时的位置信息和待嵌入的位信息，然后通过附加约束的方法将分散隐藏的位信息嵌入到FPGA的电路设计结构当中；最后，通过实验测试和性能分析，该算法不仅能以较少的实际嵌入量来标识更多的水印版权信息，而且大大降低了水印嵌入所带来的性能影响．此外，通过与现有的FPGA水印算法的实验比较，结果表明，提出的算法相对于其他的方法而言，具有水印容量大、资源开销小以及安全性能较高等优点．

英文摘要：

In order to increase watermark amount and watermark security, this paper has analyzed existing FPGA （field programmable gate array） based IP （intellectual property） watermarking techniques and presented a high-capability scattered IP watermarking algorithm in FPGA design. First of all, the algorithm adopts watermark preprocess mechanism for data compression. The mechanism uses compression function for constructing specific linear combination expressions with the encrypted information. The mechanism is not brought to the original design any additional hardware overhead. Secondly, the specific linear combination expressions are then transformed into watermark positions and bit information for being embedded while the watermark is embedded. The bit information are scattered into FPGA circuit by the additional constraint methods. The purpose of this approach is to make it very difficult for illegal user to find the location of the watermark embedding. Finally, through the experimental tests and performance analysis, the algorithm can not only use less embedded bit information amount to mark more watermark information, but also greatly reduce the impact on the system performance because of the embedded watermark information. In addition, through the experimental comparison with existing IP watermarking algorithm in FPGA design, the results show that the proposed algorithm relative to other methods, has a larger capacity of watermark information, a smaller resource overhead, and a better safety performance.