中文摘要：

指令压缩技术能够克服传统超长指令字（very long instruction word, VLIW）结构的指令高速缓冲（cache）中长指令字密度低的缺陷，使长指令字中的各条指令能紧密地排列在高速缓冲行（cacheline）中，但可能导致长指令字分置于两个cache1ine，使其不能同时参与取指与发射，从而成为处理器的性能瓶颈．受到分置cacheline的影响，传统提升循环效率的软件流水方法性能下降．高性能变长指令发射窗的机制能够解决分离指令字带来的取指发射问题，为取指流水线提供高效连续的指令流，特别地，该机制缓存循环的一次迭代，硬件支持循环的软件流水，有效地增强VLIW结构的数字信号处理器（digital signal processor，DSP）的性能．通过搭建时钟精确的处理器仿真模型，并基于DSP／IMG库上进行仿真，结果显示，采用两级指令发射窗机制，平均性能提高约21．89％．

英文摘要：

The variable-length ISA and instruction compression technology can overcome the drawback of traditional very long instruction word （VLIW） architectures. It can address the problem of low density of long instruction word by arranging the instruction word in the instruction cache with high density. However, the instruction compression technology results in separate arrangement of long instruction word into two cache lines, which makes the instruction word cannot be fetched and issued simultaneously and becomes the performance bottleneck of VLIW architecture processors. A novel high-performance variable-length instruction issue window mechanism is proposed in this paper. It solves the instruction fetch and issue problem in separating instruction words. It provides more effective and continuous instruction flow, and temporarily stores one iteration of the loop body to support software pipeline technology, which effectively improves the performance of VLIW DSP processors. By establishing the cycle-accurate processor simulator, simulation experiment is carried out based on DSP/IMG library. Experimental results show that the average performance is improved about 21.89% by adopting the proposed method. Under the TSMC 65nm technology, the area and power of the proposed mechanism increase by 0.98% and 0.76% respectively, compared with that of the core. It is suit able for VLIW architectures that have adopted instruction compression and variable-length ISA technology.