随着处理器和主存之间性能差距的不断增大,长延迟访存成为影响处理器性能的主要原因之一.存储级并行通过多个访存并行执行减少长延迟访存对处理器性能的影响.文中回顾了存储级并行出现的背景,介绍了存储级并行的概念及其与处理器性能模型之间的关系;分析了限制处理器存储级并行的主要因素;详细综述了提高处理器存储级并行的各种技术,进行了分析比较;最后分析讨论了该领域研究存在的问题和进一步的研究方向.
As the gap between processor and memory performance increases,performance loss due to long-latency memory accesses become a primary problem.Memory-level parallelism(MLP) improves performance by accessing memory concurrently.In this paper,the authors review MLP's background,then give an introduction of the conception of MLP and the relation between MLP and processor performance model,and analyze the main limitation to the processor's MLP,emphatically detail all kinds of technologies to improve processor's MLP,at last,summarize the current existing issues,and provide some further interesting directions.