中文摘要：

Resistive random access memory(RRAM) is one of the promising candidates for future universal memory.However,it suffers from serious error rate and endurance problems.Therefore,exploring a technical solution is greatly demanded to enhance endurance and reduce error rate.In this paper,we propose a reliable RRAM architecture that includes two reliability modules:error correction code(ECC) and serf-repair modules.The ECC module is used to detect errors and decrease error rate.The serf-repair module,which is proposed for the first time for RRAM,can get the information of error bits and repair wear-out cells by a repair voltage.Simulation results show that the proposed architecture can achieve lowest error rate and longest lifetime compared to previous reliable designs.

英文摘要：

Resistive random access memory （RRAM） is one of the promising candidates for future universal memory. However, it suffers from serious error rate and endurance problems. Therefore, exploring a technical solution is greatly demanded to enhance endurance and reduce error rate. In this paper, we propose a reliable RRAM architecture that includes two reliability modules： error correction code （ECC） and self-repair modules. The ECC module is used to detect errors and decrease error rate. The self-repair module, which is proposed for the first time for RRAM, can get the information of error bits and repair wear-out cells by a repair voltage. Simulation results show that the proposed architecture can achieve lowest error rate and longest lifetime compared to previous reliable designs.