中文摘要：

在深亚微米及纳米级集成电路设计过程中,电路的可靠性评估是非常重要的一个环节.本文提出了一种利用概率统计模型计算逻辑电路可靠度的方法,将电路中的每个逻辑门是否正常输出看作一次随机事件,则发生故障的逻辑门数为某个特定值的概率服从伯努利分布;再利用实验统计单个逻辑门出错时电路的逻辑屏蔽特性,根据此方法计算出ISCAS’85和ISCAS’89基准电路可靠度的一个特定范围.理论分析和实验结果表明所提方法是准确和有效的.

英文摘要：

Reliability estimation of logical circuit is becoming an important feature in the design process of deep submicron and nanoscale systems. In this paper,a reliability calculation method of logical circuit based on probability statistical model is proposed. Based on this model,the correctness of every logic gate is regarded as random event and obeying Bernoulli distribution.M eanwhile,simulation experimental results are given to analyze the logical masking properties of the circuit when only one gate set as faulty. To validate the proposed methodology we have studied the reliability range of ISCAS＇85 and ISCAS ＇89benchmark circuits. Theoretical analysis and experimental results showour method is accurate and efficient.