中文摘要：

为了降低传统增量型Σ-ΔADC在同精度情况下的量化时钟周期数,提高转换速率,提出了1种采用粗细量化的2步式增量放大型ADC.该ADC采用SAR ADC先进行6位粗量化,再采用增量型Σ-ΔADC进行8位高精度位的细量化,通过数字码拼接完成最终量化结果.同时引入了1种增益自举C类反相器技术,有效地降低了供电电压和整体功耗.该ADC使用0.18μm标准CMOS工艺进行了电路实现,在1.2 V供电电压,1 MHz采样频率、10 k S/s的转换速率的情况下,达到了81.26 d B的信噪失真比（SNDR）和13.21位的有效位数（ENOB）,最大积分非线性为0.8 LSB.并且该ADC的整体功耗为197μW,可用于低电压低功耗的仪器测量和传感器等领域.

英文摘要：

Aiming at reducing conversion time and increasing ADC speed while remaining high precision of the traditional incremental Σ-Δ ADC,a two-step zoom incremental ADC is presentde, which is realized in the standard 0.18 μm CMOS technology. The SAR ADC and incremental Σ-Δ ADC were used as 6 bits coarse converter and 8 bits fine converter in this ADC, respectively. Furthermore, the final conversion result obtained from splicing the results of the coarse converter and fine converter. In order to reduce supply voltage and power consumption, the gain-boost class-C inverter was applied in this ADC.This ADC operates in 1.2 V supply voltage, and achieves 81.26 d B SNDR and 13.21 bit ENOB at 10 k S/s conversion rate with a 1 MHz sampling frequency. The maximum integral nonlinearity（INL） is 0.8LSB. In addition, its power consumption is 197 μW, which is particularly suitable for low-voltage highresolution instrumentation, measurement and sensors applications.