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A capacitor-free high PSR CMOS low dropout voltage regulator
  • 期刊名称:Journal of Semiconductors
  • 时间:2014.6
  • 页码:065004-1-065004-5
  • 分类:TM44[电气工程—电器] TN912.3[电子电信—通信与信息系统;电子电信—信息与通信工程]
  • 作者机构:[1]Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China, [2]Superpix Micro Technology Co. Ltd, Beijing 100085, China
  • 相关基金:Project supported by the National Natural Science Foundation of China (Nos. 61036004, 61234003, 61221004).
  • 相关项目:90纳米以下高性能CMOS图像传感器关键技术研究
中文摘要:

This paper presents a capacitor-free CMOS low dropout voltage regulator which has high PSR performance and low chip area. Pole splitting and gm boosting techniques are employed to achieve good stability. The capacitor-free chip LDO was fabricated in commercial 0.18 m CMOS technology provided by GSMC(Shanghai,China). Measured results show that the capacitor-free LDO has a stable output voltage 1.79 V, when supply voltage changes from 2.5 to 5 V, and the LDO is capable of driving maximum 100 mA load current. The LDO has high power supply rejection about..79 dB at low frequency and..40 dB at 1 MHz frequency, while sacrifice of the LDO’s active chip-area is only smaller than 0.02 mm2.

英文摘要:

This paper presents a capacitor-free CMOS low dropout voltage regulator which has high PSR perfor- mance and low chip area. Pole splitting and gm boosting techniques are employed to achieve good stability. The capacitor-free chip LDO was fabricated in commercial 0.18μm CMOS technology provided by GSMC (Shanghai, China). Measured results show that the capacitor-free LDO has a stable output voltage 1.79 V, when supply voltage changes from 2.5 to 5 V, and the LDO is capable of driving maximum 100 mA load current. The LDO has high power supply rejection about -79 dB at low frequency and -40 dB at 1 MHz frequency, while sacrifice of the LDO's active chip-area is only smaller than 0.02 mm2.

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