中文摘要：

针对各种响应情况（过阻尼、欠阻尼、临界阻尼），给出了斜阶跃信号激励下的RLC互连线时延模型．该模型计算所得的结果与SPICE仿真结果的误差小于3％．时延解析式的提出，给实际电路（信号为斜阶跃的，而非理想阶跃）的时延分析带来方便．

英文摘要：

Analytical delay models for RLC interconnects under ramp input were presented. With different situations, i.e. overdamped, underdamped and critical response, delay estimates using analytical models presented in this paper are within 3 % of SPICE-computed delay. These models help a lot in delay analysis of actual circuit, while the input signal is ramp but not ideal step input.