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一种基于时延和功耗双重优化目标的布局算法
  • 期刊名称：上海交通大学学报,第41卷第5期，689-692页，2007年5月
  • 时间：0
  • 分类：TN402[电子电信—微电子学与固体电子学]
  • 作者机构：[1]上海交通大学电子工程系,上海200240
  • 相关基金：国家自然科学基金委创新研究群体基金（90207010）,华为科技基金资助项目
  • 相关项目：片上系统的互连问题与高端IP核研究
关键词： 超大规模集成电路, 布局, 时延, 功耗, 互连线, very large scale integrated circuits, placement, timing-driven, power dissipation, interconnect
中文摘要：

针对标准单元模式的超大规模集成电路布局问题,提出一种新的基于时延和功耗双重优化目标的布局算法.在以优化时延为目标函数的布局结果基础上,进一步降低芯片的功耗特性,并通过算法设计较好地解决了两者优化方向的一致性.通过标准单元测试电路的实验结果表明,该算法在时延及功耗优化方面综合性能良好.

英文摘要：

Facing the severe challenges of placement in very large scale integrated circuits based on standard cell, a new placement algorithm based on both timing-driven and power minimized optimization objective was presented. Based on the placement result which was optimized by timing-driven objective, the power dissipation of the circuit was minimized, Besides, this optimization method was well adopted to combine the timing-driven optimization and power minimization. According to the experimental results of MCNC （microelectronics centre of north -Carolina） standard cell benchmarks, the longest path delay and power dissipation are both improved.

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