中文摘要：

针对600V以上SOI高压器件的研制需要，分析了SOI高压器件在纵向和横向上的耐压原理。通过比较提出薄膜SOI上实现高击穿电压方案，并通过仿真预言其可行性。在埋氧层为3um，顶层硅为1．5um的注氧键合（Simbond）SOI衬底上开发了与CMOS工艺兼容的制备流程。为实现均一的横向电场，设计了具有线性渐变掺杂60um漂移区的LDMOS结构。为提高纵向耐压，利用场氧技术对硅膜进行了进一步减薄。流片实验的测试结果表明，器件关态击穿电压可达600V以上（实测832V），开态特性正常，阈值电压提取为1．9V，计算开态电阻为50Ω．mm2。

英文摘要：

In order to fabricate over 600 V high voltage devices on the SOI wafer, the withstand voltage theory of the SOI device was analyzed from horizontal and vertical aspects. Realization of high voltage on thin film SOI was proposed and verified processes were designed and implemented successfully with 1.5 um top silicon and 3 um buried oxide layer by simulation. CMOS compatible SOI LDMOS on Simbond （SIMOX and bonding） SOI wafers An optimized 60 um drift region implant mask was designed to realize a linearly graded doping profile, and silicon thickness in the drift region was reduced further by the thick field oxide process. The results show that the off-state breakdown voltage of SOI LDMOS is 832 V, the threshold voltage is 1.9 V, and the specific on-resistance is 50 Ω· mm2.